View SP5611_339213.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SP5611
1*3GHz Bidirectional I C Bus Controlled Synthesiser
2
Advance Information
DS3758 ISSUE 5.0 June 1998
The SP5611 is a single chip frequency synthesiser designed for TV tuning systems. Control data is entered in the standard I2C BUS format. The device contains 4 addressable bidirectional open collector ports, one of which is a 3-bit ADC. The information on these ports can be read via the I2 C BUS. the device has 4 programmable addresses, programmed by applying a specific input voltage to the P3 address select input. This enables two or more synthesisers to be used in a system.
Ordering Information
SP5611 KG/MPAS (Tubes) SP5611S KG/MPAD (Tape and reel)
FEATURES I Complete 1*3GHz Single Chip System I High Sensitivity RF Inputs
CHARGE PUMP CRYSTAL Q1 CRYSTAL Q2 SDA SCL
1 2 3 4 5 6 7 8
16 15 14 13
DRIVE OUTPUT VEE RF INPUT RF INPUT VCC NC P3 ADD SELECT PORT I/O PORT P4
I I I I I I I I I I I
Programmable via I2C BUS Low Power Consumption (5V, 20mA) Low Radiation Phase Lock Detector Varactor Drive Amp Disable 4 Bi-directional Controllable Outputs 5-Level ADC Variable I2C BUS Address for Multi-tuner Applications ESD Protection: 4kV, Mil-Std-883C, Method 3015 (1) Switchable 4512/1024 Reference Divider Pin and Function Compatible with SP5511S
(2)
SP5611
12 11 10 9
I/O PORT P7
* I/O PORT P6
I/O PORT P5
MP16
= Logic level I/O port * = 3-bit ADC input
Fig. 1 Pin connections - top view
(1) Normal ESD handling precautions should be observed. (2) The SP5511S does not have a switchable reference division ratio.
APPLICATIONS I Satellite TV I Cable Tuning Systems
I VCRs
THERMAL DATA
uJC = 41C/W uJA = 111C/W
SP5611
Advance Information
ELECTRICAL CHARACTERISTICS
TAMB = 240C to 185C, VCC = 14*5V to 15*5V, reference frequency = 4MHz. These Characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Value Characteristic Pin Min. Supply current Prescaler input voltage Prescaler input impedance Prescaler input capacitance SDA, SCL Input high voltage Input low voltage Input high current Input low current Leakage current SDA Output voltage Charge pump current low Charge pump current high Charge pump output leakage current Charge pump drive output current Charge pump amplifier gain Recommended crystal series resistance Crystal oscillator drive level Crystal oscillator negative resistance External reference input frequency External reference input amplitude Output Ports P4-P7 sink current P4-P7 leakage current Input Ports P3 input current high P3 input current low P4, P5, P7 input voltage low P4, P5, P7 input voltage high P6 input current high P6 input current low 12 13,14 13,14 13, 14 4,5 4,5 4,5 4,5 4,5 4 1 1 1 16 650 6 170 65 500 6400 10 2 2 2 2 9-6 9-6 10 10 9,8,6 9,8,6 7 7 750 2 70 10 10 1 20*5 0*8 2*7 110 210 80 1000 8 200 200 Parallel resonant crystal (note 2) mV p-p MHz AC coupled sinewave mVrms AC coupled sinewave mA A mA mA V V A A VOUT = 0*7V VOUT = 13*2V V pin 10 = VCC V pin 10 = 0V 3 0 Typ. 20 12*5 50 2 5*5 1*5 10 210 10 0*4 Max. 27 300 VCC = 4*5V to 5*5V (note 1) mA mVrms 50MHz to 1*3GHz sinewave, see Fig. 5 pF V V A A A V A A nA A Units Conditions
Input voltage = VCC Input voltage = 0V When VCC = 0V Sink current = 3mA Byte 4, bit 2 = 0, pin 1 = 2V Byte 4, bit 2 = 1, pin 1 = 2V Byte 4, bit 4 = 1, pin 1 = 2V V pin 16 = 0*7V
See Table 3 for ADC levels
NOTES 1. Maximum power consumption is 150mW with VCC = 5*5V and all ports off. 2. Resistance specified is maximum under all conditions.
2
Advance Information
ABSOLUTE MAXIMUM RATINGS
All voltages are referred to VEE and pin 3 at 0V Parameter Pin Min. Supply voltage RF input voltage Port voltage 12 13,14 6-9 6-9 Total port output current Address select voltage RF input DC offset Charge pump DC offset Drive output DC offset Crystal oscillator DC offset SDA, SCL input voltage 6-9 10 13-14 1 16 2 4,5 20*3 20*3 20*3 20*3 20*3 20*3 20*3 Storage temperature Junction temperature 255 20*3 20*3 20*3 Value Max. 7 2*5 14 6 50 V CC 10*3 V CC 10*3 V CC 10*3 V CC 10*3 V CC 10*3 V CC 10*3 6 1 150 1 150 V V p-p V V mA V V V V V V V C C Units
SP5611
Conditions
Port in off state Port in on state
13
PREAMP PRESCALER
OSC
RF IN
14
48
15-BIT PROGRAMMABLE DIVIDER
FPD
PHASE COMP
FCOMP
2
DIVIDER
Q1 CRYSTAL Q2 CHARGE PUMP
F
LOCK DET
4512/1024
3
1
POWER ON DET POR
5
15-BIT LATCH DIVIDE RATIO
DN CHARGE PUMP FL UP CONTROL DATA LATCHES AND CONTROL LOGIC
4 16
DRIVE/ VARICAP OUT
SCL SDA
I 2C BUS
4
TRANSCEIVER
CP
TO
OS
ADDRESS SELECT
3-BIT ADC
LEVEL 3 TTL COMP
4-BIT LATCH PORT INFO
4
PORT OUTPUT DRIVERS
15
VCC VEE
10
9
8
7
6
P3 ADD SELECT
P4
P5
P6
P7
Fig. 2 Block diagram
3
SP5611
Advance Information
from 512 to 1024, and is controlled by bit 7 of byte 4 (TS0); a logic 1 to 512, a logic 0 for 1024. The SP5611 differs from the SP5511 in this respect, only 512 being available on the SP5511. Note that the comparison frequency is 7*8125kHz when a 4MHz reference is used, and divide by 512 is selected. Bit 2 of byte 4 of the programming data (CP) controls the current in the charge pump circuit, a logic 1 for 170A and a logic 0 for 50A, allowing compensation for the variable tuning slope of the tuner and also to enable fast channel changes over the full band. When the device is frequency locked, the charge pump current is internally set to 50A regardless of CP. Bit 4 of byte 4 (T0) disables the charge pump when it is set to a logic 1. Bit 8 of byte 4 (OS) switches the charge pump drive amplifier's output off when it is set to a logic 1. Bit 3 of byte 4 (T1) enables various test modes when set high. These modes are selected by bits 5, 6 and 7 of byte 4 (TS2, and TS1, TS0) as detailed in Table 5. When T1 is set low, TS2 and TS1 are assigned a `don't care' condition, and TS0 selects the reference divider ratio as previously described. Byte 5 programs the output ports P4 to P7; a logic 0 for a high impedance output and a logic 1 for low impedance (on).
FUNCTIONAL DESCRIPTION
The SP5611 is programmed from an I2 C Bus. Data and Clock are fed in on the SDA and SCL lines respectively, as defined by the I2C Bus format. The synthesiser can either accept new data (write mode) or send data (read mode). The LSB of the address byte (R/W) sets the device into write mode if it is low and read mode if it is high. The Tables in Fig. 3 illustrate the format of the data. The device can be programmed to respond to several addresses, which enables the use of more than one synthesiser in an I2C Bus system. Table 4 shows how the address is selected by applying a voltage to P3. When the device receives a correct address byte, it pulls the SDA line low during the acknowledge period, and during following acknowledge periods after further data bytes are programmed. When the device is programmed into the read mode, the controller accepting the data must pull the SDA line low during all status byte acknowledge periods to read another status byte. If the controller fails to pull the SDA line low during this period, the device generates an internal STOP condition, which inhibits further reading.
WRITE Mode (Frequency Synthesis)
When the device is in write mode bytes 2 and 3 select the synthesised frequency, while bytes 4 and 5 control the output port states, charge pump, reference divider ratio and various test modes. Once the correct address is received and acknowledged, the first bit of the next byte determines whether that byte is interpreted as byte 2 or 4; a logic 0 for frequency information and a logic 1 for control and output port information. When byte 2 is received the device always expects byte 3 next. Similarly, when byte 4 is received the device expects byte 5 next. Additional data bytes can be entered without the need to re-address the device until an I2C stop condition is recognised. This allows a smooth frequency sweep for fine tuning or AFC purposes. If the transmission of data is stopped mid-byte (for example, by another device on the bus) then the previously programmed byte is maintained. Frequency data from bytes 2 and 3 are stored in a 15-bit register and used to control the division ratio of the 15-bit programmable divider. This is preceded by a divide-by-8 prescaler and amplifier to give excellent sensitivity at the local oscillator input, see Fig. 5. The input impedance is shown in Fig. 7. The programmed frequency can be calculated by multiplying the programmed division ratio by 8 times the comparison frequency FCOMP. When frequency data is entered, the phase comparator, via a charge pump and varicap drive amplifier, adjusts the local oscillator control voltage until the output of the programmable divider is frequency and phased locked to the comparison frequency. The reference frequency may be generated by an external source capacitively coupled into pin 2, or provided by an onchip crystal controlled oscillator. The comparison frequency FCOMP is derived from the reference frequency via the reference divider. The reference divider division ratio is switchable
READ Mode
When the device is in read mode the status byte read from the device on the SDA line takes the form shown in Table 2. Bit 1 (POR) is the power-on reset indicator and is set to a logic 1 if the VCC supply to the device has dropped below 3V (at 25C), for example, when the device is initially turned on. The POR is reset to 0 when the read sequence is terminated by a stop command. When POR is set high (at low VCC), the programmed information is lost and the output ports are all set to high impedance. Bit 2 (FL) indicates whether the device is phase locked, a logic 1 is present if the device is locked, and a logic 0 if the device is unlocked. Bits 3, 4 and 5 (I2, I1, I0) show the status of the I/O Ports P7, P5 and P4 respectively. A logic 0 indicates a low level and a logic 1 a high level. If the ports are to be used as inputs they should be programmed to a high impedance state (logic 1). These inputs will then respond to data complying with TTL type voltage levels. Bits 6, 7 and 8 (A2, A1, A0) combine to give the output of the 5-level ADC. The ADC can be used to feed AFC information to the microprocessor from the IF section of the receiver, as illustrated in the typical application circuit.
APPLICATION
A typical application is shown in Fig. 4. All input/output interface circuits are shown in Fig. 6. The SP5611 is function and pin equivalent to the SP5511 device apart from the switchable reference divider, and has much lower power dissipation, improved RF sensitivity and better ESD performance.
4
Advance Information
SP5611
MSB Address Programmable divider Programmable divider 1 0 2
7
LSB 1 2
14 6
0 2
13 5
0 2
12 4
0 2
11 3
MA1 MA0 2
10 2
0 2
8 0
A A A A A
Byte 1 Byte 2 Byte 3 Byte 4 Byte 5
2 2
9 1
2
2
2
2
2
2
Charge pump and test bits 1 I/O port control bits P7
CP P6
T1 P5
T0 P4
TS2 TS1 TS0 OS X X X X
Table 1 Write data format (MSB transmitted first)
Address Status byte 1 1 0 I2 0 I1 0 I0 MA1 MA0 A2 A1 1 A0 A A Byte 1 Byte 2
POR FL
Table 2 Read data format
A2 1 0 0 0 0 A1 0 1 1 0 0 A0 0 1 0 1 0 Voltage input to P6 0*6VCC to 13*2V 0*45VCC to 0*6VCC 0*3V CC to 0*45VCC 0*15VCC to 0*3VCC 0V to 0*15VCC MA1 MA0 Address select input voltage 0 0 1 1 0 1 0 1 0V to 0*1VCC Open circuit 0*4VCC to 0*6VCC 0*9VCC to VCC
Table 3 ADC levels
T1 0 0 1 1 1 1 1 TS2 TS1 TS0 X X 0 0 1 1 1 X X 0 1 0 0 1 0 1 X X 0 1 X
Table 4 Address selection
Operation mode description
Normal operation, test modes disabled, reference divider ratio = 1024 Normal operation, test modes disabled, reference divider ratio = 512 Charge pump source (down). Status bit FL set to 0 Charge pump sink (up). Status bit FL set to 1 Ports P4, P5, P6, P7set to state X Port P7 = FPD/2; P4, P5, P6 set to state X Port P7 = FPD; P6 = FCOMP; P4, P5 set to state X
NOTES X = don't care For further details of test modes, see Table 6
Table 5 Operation modes
A MA1, MA0 CP T1 T0 TS2, TS1, TS0 OS P7, P6, P5, P4, POR FL I2, I1, I0 A2, A1, A0 X
: : : : : : : : : : : : :
Acknowledge bit Variable address bits (see Table 4) Charge Pump current select Test mode selection Charge pump disable Operation mode control bits (see Table 5) Varactor drive Output disable Switch Control output port states Power On Reset indicator Phase lock detect flag Digital information from ports P7, P5 and P4 respectively 5-level ADC data from P6 (see Table 3) Don't care
Fig. 3 Data formats
5
SP5611
112V
Advance Information
112V
IF SIGNAL P7 BAND INPUTS P5 P4 P3
9 10 8 7 6 5
IF SECTION
AFC OUT
P6 15V SCL I 2C BUS SDA 4MHz CRYSTAL 18p
TUNER
1n OSCILLATOR OUTPUT 0*1
15V
11 12
SP5611
13 14 4 3 2 1
CONTROL MICRO
1n 130V
15 16
22k VARICAP INPUT 47k 10k 10n BCW31 VT
39n 180n 22k
Fig. 4 Typical application
300
VIN (mV RMS INTO 50 )
37*5
OPERATING WINDOW
25
12*5
50
500
1000
1300
1500
FREQUENCY (MHz)
Fig. 5 Typical input sensitivity
6
Advance Information
SP5611
VREF
VCC
3k
3k
CHARGE PUMP
RF INPUTS 150 DRIVE OUTPUT OS (O/P DISABLE)
RF input
Loop amplifier
VCC
VCC
67k
3k SCL/SDA CRYSTAL Q1
*
ACK
CRYSTAL Q2
* ON SDA ONLY
Reference oscillator SCL and SDA inputs
VCC VCC
30k 3k PORT P3 10k 3k
Ports P7-P4
P3 address select
Fig. 6 SP5611 input/output interface circuits
7
SP5611
Advance Information
j1 j 0.5 j2
j 0.2 j5
0
0.2
0.5
1
2
5
1*25GHz
2j 5 2j 0.2
S11:ZO = 50 NORMALISED TO 50
2j 2 2j 0.5 2j 1
FREQUENCY MARKER STEP = 250MHz
Fig. 7 Typical input impedance,
APPLICATION NOTES
An application note, AN168, is available for designing with synthesisers such as the SP5611. It covers aspects such as loop filter design, decoupling and I2C bus radiation problems. The application note is published in the Zarlink Semiconductor Media IC Handbook. A generic test/demonstration board has been produced, which can be used for the SP5611. A circuit diagram and layout for the board are shown in Figs. 8 and 9. The board can be used for the following purposes: (A) Measuring RF sensitivity perfomance (B) Indicating port function (C) Synthesising a voltage controlled oscillator (D)Testing external reference sources The programming codes relevant to these tests are given in Table 6.
EXTERNAL REFERENCE 15V R11 3k S1 S2 SK2 C7 100n C3 47n C2 220n R7 22k R12 1k X1 4MHz C1 18p
1 2 16 15 14 13
15V P2 C8 100n
130V C9 100n
112V
C6 10n (NOT FITTED, SEE NOTE)
R8 22k R9 10k TR1 2N3904 R10 47k C14 10n C5 1n C4 1n 112V SK1 RFINPUT 15V R13 12k R14 22k P3 VAR GND
TP1 DATA/SDA C12 100p
3 4 5 6
SP5611
12
C10 1n
11 10 9
CLOCK/SCL C13 100p
7 8
TR2 2N3906
ENABLE/ADDRESS SEL P1 P4
NOTE To use an external reference, capacitor C6 must be fitted and capacitor C1 removed from the board.
R1 4*7k
R2 4*7k
R3 4*7k
R4 4*7k
R5 4*7k
R6 4*7k
D1 PIN NO. 6
D2
7
D3
8
D4
9
D5
10
D6
11
112V C11 1n
Fig. 8 Test board circuit
8
Advance Information
SP5611
TP1 = PIN 3 DC BIAS
Top view (ground plane)
Underside (surface mounted components side)
NOTES 1. CIRCUIT SCHEMATIC IS SHOWN IN FIG. 8 2. ALL SUFACE MOUNT COMPONENTS ARE MOUNTED ON UNDERSIDE OF BOARD
Fig. 9 Test board layout
9
SP5611
TEST MODES
Advance Information
NOTE: When looking at FPD or FCOMP signals from ports P7 and P6. byte should be sent twice, first to set the desired reference division ratio then to switch on the chosen test mode. The pulses can then be measured by simply connecting an oscilloscope or counter to the relevant output pin on the test board. Hex code (byte 4) Operation mode description CP high mode CP low mode 8C 8E A2 A6 AA AE 9E 8F 9F
As explained in the functional description, The SP5611 can be programmed into a numb er of test modes. These are invoked by programming Hex codes into byte 4, those most commonly used being shown in Table 6. Other codes will also apply due to don't care conditions, which are assumed to be 1 in the Table.
Normal operation, reference divider ratio = 1024 Normal operation, reference divider ratio = 512 Charge pump source (down), FL set to 0 Charge pump sink (up), FL set to 1 Port P7 = FPD/2 Port P7 = FPD, P6 = FCOMP Charge pump disable, reference divider ratio = 512 Varactor line disable, reference divider ratio = 512 Charge pump and varactor linedisable, reference divider ratio = 512
CC CE E2 E6 EA EE DE CF DF
Table 5 Operation modes
10
For more information about all Zarlink products visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request.
Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in an I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2002, Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE

▲Up To Search▲

Price & Availability of SP5611

	To Download SP5611 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .